I Made Claude Read a 30-Year-Old IBM Patent on a 'Computer With No Instruction Set'

In the first post (Introduction), I described the meta-method: have an LLM read the long-form documents that humans don't. Starting from this post, I actually do it.

This is Patent Archaeology #1 — the live archaeology log of a single expired US patent that I made Claude read for real.

The Punchline

A 1995 IBM patent on a "Zero Instruction Set Computer" (a neural network chip with no instruction set) is now fully in the public domain. And the design philosophy and problem framing overlap with what is currently called "state-of-the-art" NPU/TPU work, in ways that are striking.

• Patent number: US 5,717,832
• Inventors: Andre Steimle, Pascal Tannhof, Guy Paillet (IBM France Research Lab)
• Filed: June 7, 1995 (priority date July 28, 1994)
• Granted: February 10, 1998
• Expired: June 7, 2015 (Expired – Lifetime)

This article is what came out when I made Claude read the full text of that 30-year-old IBM patent and asked it: where exactly does the modern NPU show up here?

1. How I Picked This One Patent (a reproducible pipeline)

What I did today:

1. Search Google Patents:
   "neural network chip" assignee:"International Business Machines"
   filing:1990-2000 status:"Expired"
2. Eyeball the results, pick 5 with attention-grabbing titles
3. WebFetch each Google Patents page for:
   - Title / Abstract / Claim 1 / Status / Forward citations
4. Ask Claude: "Of these five, which one is closest in mechanism
   to a modern NPU/TPU paper, and why?"
5. Narrow to one

The clear winner of the five was ZISC, US 5,717,832. The reasons:

• The provocative name — "Zero Instruction Set Computer," explicitly claiming a third architecture next to CISC and RISC
• One of the earliest patents that burns a Radial Basis Function (RBF) neural network directly into silicon
• 36 neurons per chip, with multi-chip cascade reaching thousands of neurons
• Fully expired (Lifetime expiration on June 7, 2015)

2. What the Patent Actually Is (Claude's structured summary)

The first prompt I sent to Claude after WebFetching the patent:

Extract the following from this patent:
1. Patent number, grant date, filing date, inventors, assignee
2. Status (Expired or not) and expiration date
3. Abstract
4. Main Claim 1 (independent claim 1)
5. The problem it solves
6. The proposed solution mechanism
   (neuron structure, distance calculation, classification categories, etc.)
7. Application domains and industries
8. Cited prior art
9. Forward citation count (how many later patents cite this one)
10. Description of key Figures, and which figure best represents the mechanism

The summary that came back (raw):

Problems solved

• Eliminate dependency on a microcontroller supervisor
• Overcome I/O pad constraints when scaling neuron count
• Limited inter-neuron communication flexibility
• Reduce the need for complex sort algorithms
• Lack of scalability

Solution: 3-layer RBF-based architecture

• Input layer: receives input vector components
• Hidden layer: array of neuron circuits, each computing distance D
• Output layer: classification result

Key mechanism

• Each neuron has its own R/W memory storing a prototype vector
• Similarity is judged via Manhattan distance or square distance
• Active Influence Field (AIF) is dynamically tunable
• Daisy-chain circuit manages neuron state
• Local responses aggregated by an OR circuit into a global response

Reading that for the first time, I went cold on line three.

3. Why It's "Eerily Close"

Map the above against modern NPU/TPU design vocabulary, and the shared problem framing becomes visible:

"The basic principles of the modern NPU were almost entirely written by IBM France Research Lab in 1995" would be overstating it. ZISC is an RBF-based classification chip; modern TPUs are large-scale matrix-multiply accelerators — the design targets differ substantially. But on the level of problem framing — "run neural processing autonomously in dedicated hardware" — the convergence is striking.

In particular, the line "eliminate dependency on a microcontroller supervisor." When Jeff Dean's team published the TPU paper in 2017, they framed a similar direction of problem at a much larger scale: "data center inference is too slow when it depends on the CPU." (Note: the TPU paper describes the TPU as a coprocessor that receives instructions from a host — it's not fully supervisor-free in the ZISC sense. But the direction of decoupling NN processing from general-purpose CPU is the same.) That problem direction, ZISC had named 22 years earlier.

4. Why It Was Forgotten (my speculation)

This part is speculation — it's not in the patent text.

Neural network chips in the 1990s could not build a market. Three reasons:

1. No training data. Before ImageNet (2009), there was no real benchmark to train at scale.
2. Weak training algorithms. Backpropagation existed, but no efficient way to put RBF networks on a large-scale training pipeline.
3. No application that needed the chip. OCR and speech recognition of the era were already bottlenecked by software accuracy; there was almost no demand for hardware acceleration yet.

As a result, IBM could not commercialize this technology, and in 2013 transferred it to a company called IN2H2. IN2H2 (later General Vision / CogniMem) kept selling small volumes of ZISC-derived chips, but never reached the mainstream.

Then, in 2015, the patent expired — and the design entered the public domain, free for anyone to use.

Three years later, the 2018-onwards NPU/TPU boom rediscovered overlapping problem framings as "new inventions." Google Patents shows forward citations from later patents, but the mainstream DNN accelerator literature does not directly cite this work.

5. What This Means for AI Archaeology

This is the core point of the series.

"Inside expired patents are ideas that were just 20-30 years too early — but were already the right answer."

This is structurally the same thing Gipp discovered through Amazon arbitrage. The difference is the application: instead of "Amazon products," the application here is a translation note from the past into modern AI engineering vocabulary.

The ZISC patent, when read by a modern NPU engineer, looks like the parent generation of the paper they're writing this year. Translating it across that gap hits three reader layers at once:

• Semiconductor cluster: surprise that "IBM was doing this 30 years ago"
• AI researchers: a re-framing of the historical position of their own RBF implementations
• General readers: a loosening of the "AI is something brand new" myth

A textbook example of zero freshness as a weapon.

6. Pitfalls (the ones I personally hit today)

Pitfall 1: Verifying expiration status

The "Status" field on Google Patents is reliable, but lifetime expiration and abandonment are not the same thing:

• Lifetime expiration: 20 years passed, expired naturally (free to use)
• Abandonment: holder didn't pay maintenance fees, expired (free to use)
• Lapsed for fees: unpaid → may be revived

ZISC was Expired – Lifetime, so no problem. But skipping this check is how live patents get misread as expired.

Pitfall 2: Assignment history

ZISC moved IBM → IN2H2 (2013) → expired (2015). After expiration the patent is public domain, but whether the assignee company holds related/derivative patents that are still alive is a separate check. General Vision / CogniMem's current portfolio needs its own pass.

Pitfall 3: I forgot to pull forward citations

I did not pull this patent's forward citation list today (i.e., later patents that cite it). That's normally the metric for "how much downstream impact did this patent have on the industry." Going forward, I'll add forward citations to the extraction prompt.

7. About the Prompts

The full text of every Claude prompt used across the initial 7-episode series is consolidated in Episode 7 — Templates and the first edition of the Japanese e-book (Booth). From May 2026 onward, new episodes omit the per-post prompt section in favor of the daily-life reader audience.

8. What's Next in This Sub-Series

• Patent Archaeology #2: a late-1980s natural-language-processing patent (IBM Candide lineage?) — a direct ancestor of the LLM, dug up live
• Patent Archaeology #3: a 1990s stacked memory / TSV patent — the prehistory of HBM

Every entry will be one real archaeology log of one real patent, read by Claude.

Closing

I found ZISC by typing "expired neural network chip 1990s" into Google Patents and just looking at the list. When the name "Zero Instruction Set Computer" appeared on screen, I laughed out loud. I had never seen that architecture mentioned in any industry magazine.

Three engineers from IBM France Research Lab, plus an individual inventor named Guy Paillet. They filed this design in 1994 and never saw a major commercial success before the patent expired in 2015.

But the design survived.

And today, Claude read it, and I translated it into Japanese. 30 years late, their work might finally land somewhere useful.

That is AI Archaeology.

A Note on Precision

Verified facts:

• Full text of US5717832A retrieved from Google Patents and read by Claude
• Filing date (June 7, 1995), inventors (Steimle/Tannhof/Paillet), expiration date (June 7, 2015, Lifetime) confirmed
• RBF-based 3-layer structure, Manhattan distance, daisy chain, and AIF confirmed from patent text
• Forward citations from later patents confirmed to exist on Google Patents

Author's interpretation:

• The "shared problem framing" between ZISC and modern NPU/TPU is the author's interpretive framing, not a claim of direct technical lineage
• "Not directly cited by mainstream DNN accelerator literature" is the author's observation; an exhaustive citation search was not performed

Analogies and metaphors:

• "Daisy chain ≈ parallel control (shared direction, different structure)" and "per-neuron R/W ≈ near-data computation (a precursor framing of the CIM problem)" are conceptual analogies, not design equivalences
• "No microcontroller supervisor" vs. "Google TPU's CPU independence" is a directional analogy. The TPU is technically a coprocessor that receives instructions from a host — not fully supervisor-free in the ZISC sense

Not verified:

• Total forward citation count (visible on Google Patents but not counted in this session)
• IN2H2/General Vision/CogniMem current patent portfolio
• ZISC commercial deployment details (customer names, volumes, use cases)

Where this comparison breaks down:

• ZISC is an RBF prototype-classification chip (computing distances to fixed prototypes). Modern TPUs are large-scale matrix-multiply accelerators for DNN inference. The computation targets, scales, and design philosophies differ substantially
• "Systolic array" and "daisy chain" are not the same design. Systolic arrays implement data flow structures for matrix operations; daisy-chain manages sequential neuron state — different functions

References:

• Original patent: US5717832A on Google Patents
• ZISC overview — Wikipedia
• Experience With The IBM ZISC036 Neural Network Chip
• Successor: General Vision / CogniMem

Next up — Patent Archaeology #2: A late-1980s IBM Candide statistical machine translation patent — a direct ancestor of the LLM.

→ Read the original Japanese version at haruko's blog

Author: はる子 / @haruko_ai_jp — a non-engineer running 7 web apps with Claude Code and 4 AI assistants in Tokyo.