Hardware & Energy Patents

On July 30, 1959, Robert Norton Noyce, a Fairchild Semiconductor founding member (then 31 years old, vice president) filed 'Semiconductor device-and-lead structure' in the United States as the sole inventor. It was granted as US2981877A on April 25, 1961 and expired by lifetime on April 25, 1978. Claim 1 covers a structure in which a metal lead runs over a silicon-surface oxide layer (SiO2) and bridges a pn junction. This fenced the path to electrically isolating multiple devices on the same wafer. Kilby's US3138743A (covered in Day 17 / ep62) was filed 5 months earlier, but its Au flying-wires wiring scheme was unsuited to mass production; Noyce's oxide-isolated planar approach became the material substrate that connects continuously to modern CMOS. Original / Current Assignee both Fairchild Semiconductor Corp; Noyce is sole inventor, with an implicit dependence on Jean Hoerni's planar process patent US3025589A (Fairchild, contemporaneous, separate filing) for oxide passivation. In the 1969 patent litigation between Texas Instruments and Fairchild, the USPTO ruled that 'Noyce and Kilby are co-inventors,' and in 2000 Kilby received the Nobel Prize in Physics alone (Noyce, who died in 1990, was ineligible). As the Day 27 Cage Patents axis HW Open opening note, this article excavates (1) Claim 1 verbatim and reading the oxide isolation as an electrical cage, (2) the 5-month gap with Day 17 / ep62 Kilby and the divergence in mass-production wiring schemes, (3) the implicit dependence on Hoerni's planar process US3025589A (a separate filing), (4) positioning within the Cage axis material variations of Day 19 ep70 Masuoka flash, ep71 CCD, and ep72 HA gel, and (5) the continuity of the oxide-isolation step in modern semiconductor manufacturing — TSMC 2nm / Samsung GAA / Intel 18A in 2026.

On April 19, 1973, two Bell Telephone Laboratories researchers—Willard Sterling Boyle and George Elwood Smith—co-filed 'Buried channel charge coupled devices' in the United States, granted as US3792322A on February 12, 1974. Claim 1 covers 'a charge coupled device with a planar charge storage medium and multiple discrete electrode field plates, capable of controllably moving charge between charge-storage sites by applying appropriate electrical bias, characterized by the storage medium being bounded on all sides by electrical barriers, depleted via ohmic contact at a limited area, with potential minima existing physically within the storage medium, interior of the boundary electrical barriers.' Claim 1 verbatim writes 'potential minima existing physically within the storage medium, interior of the boundary electrical barriers,' explicitly requiring the charge cage (confining charge in a potential well) of Day 19's 'Cage Patents' axis. The Original Assignee was 'Individual,' but a Certificate of Correction retroactively assigned it to Bell Telephone Laboratories Murray Hill NJ—an unusual transfer history. Inventors, Bell Labs assignment, filing date, and grant date all match the DB (13th match confirmed). In 2009 Boyle/Smith received the Nobel Prize in Physics for the CCD invention. This memo retrieves title, inventors, assignees, dates, and Claim 1 from Google Patents, but the full specification (relationship to the 1969 Boyle/Smith Bell System Technical Journal paper, and the generational shift to CMOS image sensors) is unread.

On December 20, 1980, two researchers at Tokyo Shibaura Electric Co Ltd (now Toshiba)—Fujio Masuoka and Hisakazu Iizuka—co-filed a 'Semiconductor memory device and method for manufacturing the same' in the United States, granted as US4531203A on July 23, 1985 (US filing 1981-11-13, Japan priority 1980-12-20). Claim 1 covers a memory device whose cells, arranged in matrix form, are built from a three-layer gate structure: erase gate, floating gate, and control gate, with the third insulating film thicker than the first. This is the precursor to modern NAND flash memory, and the entire infrastructure of SSDs, smartphone storage, microSD cards, SD cards, USB memory, and LLM weight-file storage rests on the principle of confining electrons inside a floating gate, as introduced here. The patent predates the term 'flash' by four years (Masuoka coined it in his 1984 IEDM paper). Claim 1's core is the **electrical isolation of the floating gate by three layers of gates with asymmetric insulating films**, enabling separate erase, write, and read operations. Two DB corrections: (1) DB 'Masuoka solo' → reality 'Masuoka + Iizuka two co-inventors' (same pattern as Day 17 ep64 Goodenough/Mizushima, Day 18 ep68 Nakamura/Mukai/Iwasa); (2) DB '1982 grant' → reality 'grant 1985-07-23' (priority 1980-12-20, filing 1981-11-13). Day 19's three-piece set 'Cage Patents' note slot, where Claim 1 explicitly requires a structure 'a portion of said floating gate overlapping a part of said erase gate with a first insulating film being interposed' that physically confines electrons in a cage.

On July 17, 1980, Ching W. Tang of Eastman Kodak Company solo-filed 'Organic electroluminescent cell' with the US Patent Office. The patent was granted as US4356429A on October 26, 1982. Claim 1 covers an improvement to an electroluminescent cell (anode, cathode, luminescent zone between the electrodes comprising an organic luminescent agent and a binder with breakdown field strength of at least about 10⁵ V/cm), the improvement being a hole-injecting zone of a porphyrinic compound layer between the luminescent zone and the anode. Both the Original Assignee and Current Assignee are Eastman Kodak Co. The inventor is **Ching W. Tang solo** — the popular industry narrative that 'Tang & Van Slyke co-invented OLED' does not match this patent's inventor field. Steven A. Van Slyke is a co-author of the 1987 Appl. Phys. Lett. 51:913 'Organic electroluminescent diodes' paper presenting the diamine HTL + Alq3 EML two-layer structure, but he is absent from this patent's inventor field. This is the same '**divergence between paper / textbook / award reporting and patent inventor names**' pattern as Day 11 ICI beta-blockers (James Black absent), Day 12 sildenafil (some researchers absent), and Day 9 PCR (Mullis solo award vs six co-inventors). Day 8–18 has accumulated **23 corrections** with **12 match confirmations**. This memo is at primary-URL-confirmed / Claim 1 retrieved / specification full text unread stage and organizes (1) the development from single-layer porphyrin to the 1987 two-layer structure, (2) Eastman Kodak's spinoff, bankruptcy, and OLED patent succession, (3) technology transfer to Samsung Display / LG Display / Chinese BOE / TCL CSOT OLED mass-production factories, and (4) connections to foldable OLEDs (Samsung Galaxy Z Fold/Flip, Huawei Mate X, Xiaomi Mix Fold) and OLED adoption from iPhone X onward.

On November 20, 1992, three Nichia Chemical Industries Ltd researchers (Anan, Tokushima)—Shuji Nakamura, Takashi Mukai, and Naruhito Iwasa—co-filed 'Light-emitting gallium nitride-based compound semiconductor device' with the Japan Patent Office. They filed a US continuation on November 17, 1993, granted as US5578839A on November 26, 1996. Claim 1 covers a double-heterostructure GaN-based light-emitting device comprising (a) an active layer with first and second major surfaces formed of a low-resistivity In_x Ga_(1-x) N (0 less than x less than 1) compound semiconductor doped with an impurity, (b) a first clad layer of n-type GaN-based compound semiconductor having a different composition from the active layer, joined to the first major surface, and (c) a second clad layer of low-resistivity p-type GaN-based compound semiconductor having a different composition from the active layer, joined to the second major surface. The Original Assignee is Nichia Chemical Industries Ltd (the company name at filing, headquartered in Anan, Tokushima); the Current Assignee is Nichia Corporation (after the 2003 corporate name change). Among the three inventors, Shuji Nakamura is widely recognized as the inventor of the patent's core—p-type GaN crystal growth technology and the InGaN quantum well structure—but **Takashi Mukai and Naruhito Iwasa also appear as co-inventors** in the patent, so the DB entry 'Shuji Nakamura solo' is corrected. Day 8–18 has accumulated **22 corrections** with **12 match confirmations** (the correction sequence resumes after the three consecutive matches at Day 17 ep65/66 / Day 18 ep67). The DB Original Assignee 'Nichia Corporation' is also incorrect; at filing the company name was **Nichia Chemical Industries Ltd** (used 1956–2003). This memo is at primary-URL-confirmed / Claim 1 retrieved / specification full text unread stage, and organizes (1) the meaning of the three-name co-invention structure, (2) Nakamura's compensation lawsuit against Nichia (filed 2001, Tokyo District Court ¥20 billion judgment 2004, Tokyo High Court ¥840M settlement 2005), (3) the inventor-field separation in the 2014 Nobel Prize in Physics (Akasaki / Amano / Nakamura), and (4) the connections to modern Samsung / LG / Chinese BOE OLED / Mini-LED TVs and smartphone white-LED light sources.

On March 5, 1954, three researchers at Bell Telephone Laboratories—Daryl M. Chapin (electrical engineer, Basking Ridge NJ), Calvin S. Fuller (chemist, Chatham NJ, semiconductor impurity diffusion specialist), and Gerald L. Pearson (physicist, Bernards Township NJ, semiconductor physicist)—co-filed 'Solar energy converting apparatus' with the US Patent Office. Three years later, the patent was granted as US2780765A on February 5, 1957. Claim 1 covers an arrangement for utilizing solar radiation to keep a storage battery charged, comprising (a) a storage battery to be charged, (b) at least one photosensitive element including a silicon body with an n-type zone contiguous with a p-type zone including a concentration of boron impurities (with the thickness of the p-type zone of the order of the diffusion length of electrons), and (c) a unilaterally-conductive element serially connected with the storage battery and photosensitive element, poled to pass charging currents developed by the photosensitive element and to block discharging currents from the battery through the photosensitive element. The Abstract claims efficiencies exceeding 5%, marking the first practical-line crossing over the prior Charles Fritts selenium cell (1883, under 1% efficiency) and Russell Ohl's silicon p-n junction discovery patent at Bell Labs (1941, US2402662A). The Original Assignee is Bell Telephone Laboratories, Incorporated (AT&T's research subsidiary), and the Current Assignee is AT&T Corp. All inventors, assignees, priority date, and grant date match the DB entry—the 12th match confirmation in the Day 8–17 correction sequence (which has accumulated 21 corrections), following the back-to-back HW-007/008 matches in Day 17. The Patent Family was filed in the Netherlands, Switzerland, France, Germany, Japan, and the United Kingdom—six countries, reflecting Bell Labs' ambitious global rollout strategy for solar cells in the 1950s. This note examines (1) the meaning of Claim 1's three-element configuration (battery + photosensitive element + unilaterally-conductive element), (2) the relationship to Russell Ohl's 1941 silicon p-n junction discovery patent (same Bell Labs but different lineage), (3) the April 25, 1954 public demonstration at AT&T's New York headquarters with radio and telephone driven by solar power, (4) the 1958 Vanguard 1 satellite installation (NASA / US ARPA, the first major commercialization in space applications), (5) the relationship to the 1956 AT&T consent decree and the royalty-free compulsory licensing of transistor patents, (6) technology transfer from Bell Labs to Japan (Sharp's research start in 1959, commercialization in 1963), Germany (Siemens), and US RCA, (7) the material design distance to modern monocrystalline Si (Tongwei, JinkoSolar, LONGi), PERC, TOPCon, HJT, and perovskite cells, and (8) the contemporary significance of China's ~80% dominance of the solar cell supply chain (IEA 2024) viewed through the lens of this 72-year-old material foundation.

On July 14, 1967, Robert H. Dennard at IBM's T.J. Watson Research Center solo-filed 'Field-effect transistor memory' in the United States, granted on June 4, 1968 as US3387286A. Claim 1 covers an integrated circuit memory comprising multiple memory cells coupled to word lines and bit lines, each cell comprising (a) an input field-effect transistor with a channel region and a gate electrode, (b) a storage device exhibiting capacitance with one electrode connected to the transistor and the other to a reference potential, (c) a word line connected to the gate electrode, (d) a bit line connected to one terminal of the transistor, (e) control means applying voltage signals to the word line, the bit line, and the reference potential to charge the capacitance, and (f) the bit-line signal being ineffective on the capacitance unless the word-line signal renders the transistor conductive. The Abstract states that each cell is formed using a single field-effect transistor and a single capacitor, with information storage occurring through capacitor charging and periodic regeneration necessary because charge leaks over time; the body notes that, in the worst case, refresh is needed 'every 200 microseconds,' consuming about 10% of memory operation time. This patent is **the core patent fencing the minimal 1T1C (1 Transistor – 1 Capacitor) DRAM cell as of 1968**; it expired on June 4, 1985 due to US patent term. The inventor, assignee, filing year, and grant year all match the DB record (the 10th match in the Day 8–16 correction streak, the second consecutive match in Day 17 after HW-007). It must be clearly distinguished from the Dennard scaling rule formalized in Dennard's 1974 co-authored paper 'Design of ion-implanted MOSFETs with very small physical dimensions' (IEEE J. Solid-State Circuits 9(5), 256–268)—the patent is a structural invention (1T1C cell), and the scaling paper is an empirical rule (constant power density when voltage, current, and dimensions are scaled at the same ratio). This memo retrieves Claim 1, the inventor, the assignee, the dates, and the '200 µs refresh' reference from Google Patents, but the full specification (correspondence with the IBM Type 369 memory product, patent relationships with 1970s competitors such as Intel 1103 and Mostek MK4096) has not been read.

On January 22, 1973, Federico Faggin, Marcian E. 'Ted' Hoff Jr., and Stanley Mazor at Intel Corporation jointly filed 'Memory system for a multi chip digital computer' in the United States, granted on June 28, 1974 as US3821715A. Claim 1 covers a general-purpose digital computer comprising (a) a central processor on a first semiconductor chip, (b) a plurality of bidirectional data bus lines, and (c) at least separate first and second semiconductor memory chips, each defining a memory and including a chip decoding circuit that recognizes a different predetermined code on the bidirectional data bus lines and activates a portion of its memory upon receipt of the predetermined code. The Abstract describes a configuration in which a group of MOS chips (RAMs and ROMs) couple to a CPU via common bidirectional data buses; the body uses 'central processing unit,' 'MOS,' and 'single MOS chip' repeatedly, but **does not mention** Busicom or 4004 by name. This patent covers the **bus architecture of the Intel MCS-4 family (4004 CPU / 4001 ROM / 4002 RAM / 4003 shift register), not the structural patent of the 4004 alone**. The three inventors match the DB record (the 9th match in the Day 8–16 correction streak). Federico Faggin's contribution extends beyond the bus configuration in this patent to the silicon-gate MOS process (US3597469A, filed 1968 while at Fairchild) that made the 4004 manufacturable, while Masatoshi Shima, sent by Busicom as a design collaborator and deeply involved in the 4004's logic design, is **absent from this patent's inventor field**. This memo confirms the primary URL, has retrieved Claim 1, but has not read the full specification. It positions the patent as a starting point for clarifying (1) the precise interpretation of the title, (2) the distinction between 'MCS-4 family patent' and '4004-alone patent,' (3) the absence of Shima from the inventor field, and (4) the distance to modern AI-chip bus architectures (Nvidia H100, Cerebras WSE-3, China's Cambricon, Google TPU).

On April 5, 1979, John B. Goodenough, professor at Oxford's Inorganic Chemistry Laboratory, filed a UK priority application for an electrochemical cell with new fast ion conductors together with Koichi Mizuchima (a visiting researcher from the University of Tokyo). The US continuation was filed on March 31, 1980 and granted on November 24, 1981 as US4302518A. Claim 1 covers an ion conductor of the formula AxMyO2 with α-NaCrO2 layered structure (A is Li, Na, or K; M is a transition metal; x < 1, y ≈ 1) whose A+ cation vacancies have been created by A+ cation extraction. This fences the LiCoO2 (lithium cobalt oxide) layered cathode as a material patent in the United States. The Original Assignee is 'Individual,' which was transferred to the United Kingdom Atomic Energy Authority (UKAEA) in 1984, then to AEA Technology PLC in 1997, and the current assignee is Ricardo AEA Ltd. The inventor field lists only Goodenough and Mizuchima; P.C. Jones and Philip J. Wiseman, who appear as co-authors on the parallel Mater. Res. Bull. 15(6), 783–789 (1980) paper, are absent from the patent's inventor field. Sony commercialized the world's first Li-ion battery in 1991 by combining Yoshino Akira's lithium-ion intercalation graphite anode (US4668595A, 1985 filing, Asahi Kasei) with Goodenough's LiCoO2 cathode, providing the material foundation for smartphones, laptops, data center UPS systems, and electric vehicles. The 2019 Nobel Prize in Chemistry was awarded jointly to Goodenough (age 97 at the time of the award, the oldest Nobel laureate in history), M. Stanley Whittingham (TiS2 system, Exxon), and Yoshino Akira (graphite anode, Asahi Kasei). This note examines (1) the correction of DB entries claiming 'Mizushima/Jones/Wiseman co-inventors' and 'University of Oxford assignee,' (2) the divergence between paper authors and patent inventors, (3) the meaning of the 1984 UKAEA transfer, (4) the material substrate of modern AI data centers, smartphones, and EVs, and (5) design divergence with LFP/NMC/all-solid-state systems.

On February 6, 1959, in Dallas, Texas, the new Texas Instruments engineer Jack S. Kilby filed US Patent US3138743 'Miniaturized electronic circuits' as sole inventor. Claim 1 requests 'a plurality of junction transistors defined in a single-crystal semiconductor wafer (each transistor with thin opposite-conductivity layers on one major face providing base and emitter regions overlying a collector region, with the base-emitter and base-collector junctions both extending wholly to that major face) + a plurality of thin elongated regions in the wafer providing semiconductor resistors + conductive means selectively connecting them.' Background: Kilby joined TI in May 1958 and conceived the IC during the company-wide vacation period when, as a new hire, he had no vacation rights. On September 12, 1958, he assembled an oscillation circuit on a germanium mesa p-n-p transistor and confirmed continuous sine-wave output on an oscilloscope — the world's first working IC. The patent was granted June 23, 1964 and expired June 23, 1981. In parallel, Robert N. Noyce of Fairchild Semiconductor filed US2981877 'Semiconductor device-and-lead structure' on July 30, 1959 (about 5 months after Kilby), granted April 25, 1961. Noyce, building on Hoerni's planar process, achieved monolithic structure with on-chip Al wiring; whereas Kilby's chip used thin gold (Au) flying wires between elements, a hybrid structure that is, strictly speaking, not a monolithic IC. Commercial ICs followed the Noyce lineage. Kilby received half of the 2000 Nobel Physics Prize (the other half to Alferov and Kroemer for heterostructures); Noyce, having died in 1990, was ineligible. In his Nobel lecture, Kilby remarked, 'Bob ought to have been here.' This memo confirms primary source URL and Claim 1, but the full specification text remains unread. We position this as a starting point for organizing what's analogy and what's similarity in the modern China RISC-V vs. ARM vs. x86 instruction-set split.

On February 26, 1948, at Bell Telephone Laboratories in Murray Hill, NJ, physicist John Bardeen and experimentalist Walter H. Brattain filed US Serial No. 11,165 (later abandoned, parent of US2524035) titled 'three-electrode circuit element utilizing semiconductive materials.' The patent was refiled as a continuation-in-part on June 17, 1948 (Serial No. 33,466) and granted on October 3, 1950 as US2524035. The invention covers a circuit element comprising (a) a semiconductor block of one conductivity type, (b) a thin surface layer of opposite conductivity type, (c) an emitter electrode contacting the surface layer, (d) a collector electrode collecting current spreading from the emitter, and (e) a base electrode contacting the body. Claim 1 covers this 5-element combination. The design core is 'a 3-terminal semiconductor amplifying element,' which is the basic patent of the point-contact transistor. The absence of William Shockley from the inventor list reflects Bell Labs' internal division of labor: Shockley was not directly involved in the December 23, 1947 working demo, which was established by Bardeen's surface states theory and Brattain's experimental technique. Shockley filed a separate junction transistor patent US2569347 as sole inventor on June 26, 1948, granted September 25, 1951, distinct from the Bardeen-Brattain patent. The 1956 Nobel Physics Prize was awarded jointly to all three, but the patent inventorship remained at two. Furthermore, on January 24, 1956, the US v. Western Electric & AT&T antitrust consent decree placed all pre-decree Bell Labs semiconductor patents (including this one) under royalty-free compulsory licensing for all applicants (RCA/GE/Westinghouse excluded due to existing cross-licenses). This enabled Texas Instruments, IBM, Sony, Toshiba, NEC, Hitachi, Samsung, and TSMC to enter at low cost, becoming the institutional origin of global semiconductor industry diffusion (Watzinger, Fackler, Nagler & Schnitzer 2020 economic history paper rates this consent decree above Marshall Plan in economic contribution). This article excavates (1) the verbatim Claim 1 of US2524035, (2) the design split between point-contact and junction, (3) the circumstances of Shockley's absent name, (4) the institutional effect of the 1956 consent decree, (5) connection to the contemporary China-AI × Korea-Taiwan semiconductor niche, and (6) positioning as the inaugural episode of Week 4 'Hardware & Energy Patent' subseries.